PCIE Logic Level IO Standard for PCIE0 on M.2 Key M connector of Jetson NX

Hi,

In our application, we are using PCIE0 port on M.2 Key M connector (J11) of NVIDIA Jetson NX board as Root Complex port,

We need to confirm the what is Logic level IO standard used for the PCIE0 port, i.e., CML, LVPECL, LVDS etc.

We have gone through the design guide and all other design related document for the Jetson NX board, but couldn’t able to find the above information.

Please share the Logic level IO standard details for the PCIE port 0 of Jetson NX board.

Regards,

Harsh