PCIe 2024 A technology forecast for the year ahead
Last but not least, I’d like to say a few words about buses. No, not the transportation kind of bus, unless of course we’re talking about transporting data bits across interfaces, in which case…yep, those. Internal first. PCI Express (PCIe) is increasingly dominant not only in computers but also in embedded systems that leverage the same fundamental silicon building blocks. Plus, PCIe forms the technology foundation of spinoff interfaces such as the CFExpress card.
Today’s mainstream deployed PCIe variant is Gen4 (aka, 4.0), whose public unveil was more than a decade ago, believe it or not, in November 2011 (the spec was finalized in mid-2017). Its successor, Gen5 (5.0), whose spec was finalized in 2019 and which is now beginning to show up in leading-edge PCs, doubles the PCIe Gen4 bandwidth, from 31.5 GBytes/s in each direction for a 16-lane configuration to 63 GBytes/sec bidirectional.
Who needs all that speed? Good question. Graphics cards, arguably, although all but the highest end PCIe Gen4 ones available today benchmark comparably even when plugged into a backwards-compatible PCIe Gen3 slot, begging the question of what additional benefit a PCIe Gen5 successor might deliver. And SSDs, again arguably, although less so, particularly given that the M.2, U.2 and other to-system interfaces are narrower in terms of the number of parallel lanes than what’s typically found with full-size add-in cards. Still, benchmarking of initial PCIe Gen5 SSDs versus high-end Gen4 predecessors reveals only modest improvements, and then only when sequentially reading and (especially) writing short sequences of data to and from the DRAM cache onboard the flash memory module. And the incremental power draw demanded by the newer SSDs is definitely not modest. That said, PCIe Gen5 capabilities both at the system and peripheral level are forecasted to ramp into fuller production volume beginning in 2024.
And what about external interfaces? I’m talking here, in today terms, specifically about Thunderbolt 3, Thunderbolt 4, USB 3.x and USB 4. Explaining the differences between them (including scenarios when TB3 might actually perform better than its TB4 successor) is beyond the wordcount-and-other scope of this summary, although I intend to dive into detail on the topic in a dedicated writeup next year. Also to be included in it is what’s motivating the mention here: Thunderbolt 5, which Intel officially unveiled back in September.
Unlike with the Thunderbolt 3-to-4 generational transition, which maintained the same 40 Gbps bidirectional bandwidth albeit adding USB 4 compatibility and other implementation tweaks, Thunderbolt 5 marks a return to the bandwidth doubling of prior generational transitions, now 80 Gbps in each direction. Plus, a dynamically configurable feature called Bandwidth Boost allows for three of the four Thunderbolt lanes to optionally transport traffic in one direction (120 Gbps, with 40 Gbps in the other direction), supporting ultra-high resolution, ultra-high frame rate displays, for example. Still, I wonder when (if at all) mainstream applications and the hardware they run on will beg for this much speed (and low accompanying latency), considering the potential power, cost, and other tradeoffs necessary to deliver it. We’ll supposedly find out soon enough; per Intel’s release, “Computers and accessories based on Intel’s Thunderbolt 5 controller, code-named Barlow Ridge, are expected to be available starting in 2024.”