The Jetson AGX Orin Devkit PCIe Configuration

Jetson AGX Orin (Root point) and FPGA VCU 118 (end point), communicating through a pcie device, I want to modify my Jetson’s pcie controller to C5 Root point mode, how do I modify ODMDATA?

Image from： (Jetson AGX Orin Platform Adaptation and Bring-Up — Jetson Linux
Developer Guide 34.1 documentation)

Also do I need to make changes in this, what does CVB design mean here, I couldn’t find a definition on google