AGX Xavier pcie C0

Hi ,

I found that C0 controller pcie@14180000 has the property num-lanes =

in SOC dtsi which I didn’t edit anything (tegra194-soc/tegra194-soc-pcie.dtsi)

but according to adaption guide C0 only 4 lanes
https://docs.nvidia.com/jetson/archives/r35.3.1/DeveloperGuide/text/HR/JetsonModuleAdaptationAndBringUp/JetsonAgxXavierSeries.html?highlight=usb#uphy-lane-assignment

Should the num-lanes be 4 correspond to the adaption guide?

Or C0 can support to 8lanes?