Orin NX pcie clock free run

I am using Jetson Orin-NX PCIE0 x4 LANES as root-complex that connected to end-point Xilinx FPGA.

Is it possible to use free running PCIe 100Mz clock for END-POINT (FPGA) or the END-POINT (FPGA) must use 100Mz clock from Orin NX?