PCIe interface with Zynq SOC

Hello.

I want to connect jetson PCIe root port to zynq PCe endpoint, but in board, Zynq use own reference clock. Will this work?

It looks like a Figure 7-5 Jetson AGX Orin Series Design Guide.

Zynq PCIe IP not have CLKREQ and WAKE pors, only PCIe_RST.

Are these ports required for operation?