AGX Xavier PCIe PEX_CLK5 REFCLK Control
Hello!
We are having trouble with 4-lane PCIe links on our custom PCB between the AGX Xavier and PCIe switch training at Gen3 speed. Gen2 speed is successful when the switch is configured to do so, but attempts to configure for Gen3 speed result in the LTSSM dropping down to Gen1 speed. There do not appear to be any problems with the lanes, as all 4 lanes are properly read by the PCIe switch and the Jetson registers. Attempts to fix this problem by disabling ASPM and making edits to the PCI driver sources have not been successful to link train at Gen3.
The TX2 tuning guide contains registers for controlling PCIe REFCLK current and resistance values, as shown in this post: Regarding PCIE clock of Jetson TX2 - #15 by Trumany. However, this information is not contained in the AGX Xavier tuning guide or TRM documents. Do equivalent registers exist for the AGX Xavier to control PCIe PEX_CLK5?
Thanks!
Ian
