PCIe Maximum Payload Size only 128bytes

Hello,

We have a custom board with a Xavier NX + PCIe Switch + FPGA. The Jetson is the PCIe root. All endpoints are capable of >= 256 bytes and this can be confirmed through lspci as well as the switch configuration software.

I mostly do FPGA work, so I don’t work with embedded Linux much, but there must be some way of getting the Jetson to NOT limit all of the endpoints to 128byte TLPs.

I’ve tried a few kernel boot parameters such as pci=pcie_bus_safe, pci=pcie_bus_perf, etc. (set in /boot/extlinux/extlinux.conf), but I have yet to find anything that helps.

Any help would be greatly appreciated!

Thanks,

Chip