Jetson AGX Orin , JP5.1.2 and PCIE RP(C5)

When we use the Jetson AGX Orin Devkit as PCIe x8 (C5,RP) connecting to FPGA(x4, EP), it does not work.

We expected the result that it works because you mentioned below:

“If you want to use a x4 device on x8 configuration, then nothing needs to change. The default software already supported it.”
https://forums.developer.nvidia.com/t/orin-pcie/233122/3

In addition, TRM in Page 7356, “9.3.1.1 Features” says below:

• PCIe controller configurations

x8 lane configuration

Supports x8, x4, x2, and x1 links

However, it works well when we use the Jetson AGX Orin Devkit as PCIe x8 (C5,RP) connecting to FPGA(x8, EP).

Does the PCIe x8 (C5) of the J6 in the Jetson AGX Orin Devkit only support x8 links? Or we need to set up SW?

thanks